Semiconductor package



FIG. 1 is a front elevational view of a semiconductor package, showing our design;

FIG. 2 is a left side elevational view thereof;

FIG. 3 is a top plan view thereof; and,

FIG. 4 is a rear elevational view thereof.

The broken lines shown in the figures are for illustrative purposes only and form no part of the claimed design. 

The ornamental design for a semiconductor package, as shown and described. 